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| a FEATURES +50 mA Voltage Programmable Current Range 1.5 ns Propagation Delay Inhibit Mode Function High Speed Differential Inputs for Maximum Flexibility Hermetically Sealed Small Gull Wing Package Compatible with AD1321, AD1324 Pin Drivers APPLICATIONS Automatic Test Equipment Semiconductor Test System Board Level Test System High Speed Active Load with Inhibit Mode AD1315 FUNCTIONAL BLOCK DIAGRAM PRODUCT DESCRIPTION The AD1315 is a complete, high speed, current switching load designed for use in linear, digital or mixed signal test systems. By combining a high speed monolithic process with a unique surface mount package, this product attains superb electrical performance while preserving optimum packaging densities in an ultrasmall 16-lead, hermetically sealed gull wing package. Featuring current programmability of up to +50 mA, the AD1315 is designed to force the device under test to source or sink the programmed IOHPROG and IOLPROG currents. The IOH and IOL currents are determined by applying a corresponding voltage (5 V = 50 mA) to the IOH and IOL pins. The voltageto-current conversion is performed within the AD1315 thus allowing the current levels to be set by a standard voltage out digital-to-analog converter. The AD1315's transition from IOH to IOL occurs when the output voltage of the device under test slews above or below the programmed threshold, or commutation voltage. The commuta- tion voltage is programmable from 2 V to +7 V, covering the large spectrum of logic devices while able to support the large current specifications (48 mA) typically associated with line drivers. To test I/O devices, the active load can be switched into a high impedance state (Inhibit mode) electrically removing the active load from the path through the Inhibit mode feature. The active load leakage current in Inhibit is typically 20 nA. The Inhibit input circuitry is implemented utilizing high speed differential inputs with a common-mode voltage range of 7 volts and a maximum differential voltage of 4 volts. This allows for the direct interface to the precision of differential ECL timing or the simplicity of switching the Active Load from a single ended TTL or CMOS logic source. With switching speeds from IOH or Io~ into Inhibit of less than 1.5 ns, the AD1315 can be electrically removed from the signal path "on-the-fly." The AD1315 is available in a 16-lead, hermetically sealed gull wing package and is specified to operate over the ambient commercial temperature range from 0C to +70C. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997 AD1315-SPECIFICATIONS otherwise noted.) Parameter DIFFERENTIAL INPUT CHARACTERISTICS INH to INH Input Voltage, Any One Input Differential Input Range Bias Current Current Program Voltage Range IOH, 0 mA to +50 mA (Sink)1 IOL, 0 mA to -50 mA (Source)1 Input Resistance IOHRTN, IOCRTN Range2 VCOM, VDUT Range IOH, 0 mA to +50 mA IOL, 0 mA to -50 mA OUTPUT CHARACTERISTICS3 Active (Sink/Source) Mode Transfer Function Accuracy Linearity Error Gain Error Offset Error Output Current TC Inhibit Mode Output Capacitance Inhibit Leakage DYNAMIC PERFORMANCE3 Propagation Delay IMAX to INHIBIT (tPD1)4 INHIBIT to IMAX (tPD2)4 POWER SUPPLIES -VS to +VS Difference Supply Range Positive Supply Negative Supply Current Positive Supply5 Negative Supply5 Power Dissipation6 PSRR7 Min (All measurements made in free air at +25 C. +VS = +10 V, -VS = -5.2 V, unless AD1315KZ Typ Max Units Comments -3.0 0.4 -2.0 0 0 ECL 1.0 4.0 4.0 2.0 +5.0 +5.0 Volts Volts mA Volts Volts k Volts Volts Volts Volts 50 -2.0 -2.0 0.5 -2.0 +7.0 +7.0 +7.0 +4.0 VDUT - VCOM >1 V VCOM - VDUT >1 V 10 -0.12 -2.0 -1.0 10 3.0 200 +0.12 +2.0 +1.0 mA/V % FSR % FSR mA A/C pF nA See Figure 1 See Figure 1 -200 20 See Figure 2 0.5 1.5 15.2 +9.5 -5.45 +705 -1005 +10 -5.2 +85 -85 1.3 1.5 3.0 15.4 +10.5 -4.95 +100 -70 1.54 0.05 ns ns Volts Volts Volts mA mA %/% NOTES 1 IOHPROG/IOLPROG voltage range may be extended to -100 mV due to a possible 1 mA offset current. 2 IOHRTN/IOLRTN should be connected to V COM to minimize power dissipation. 3 VDUT = -2 V to +7 V, C TOTAL = 10 pF, RDUT = 10 . For inhibit leakage tests, V DUT = 0 V to +5.9 V, I OH = -4 mA, IOL = +4 mA, TCASE = +36C. 4 Measured from the ECL crossing to the 10% change in the output current. 5 IPROGRAM = 50 mA. 6 Maximum power dissipation with +V S = +10 V, -VS = 5.2 V, IPROGRAM 50 mA, VCOM = VDUT = 0 V. 7 For a 1% change in +V S or VS, the output current may change a maximum of 0.05% of Full Scale Range (FSR). Specifications subject to change without notice. -2- REV. A AD1315 ABSOLUTE MAXIMUM RATINGS 1 CONNECTION DIAGRAM Power Supply Voltage +VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V -VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -11 V Difference from +VS to -VS . . . . . . . . . . . . . . . . . . . . . 16 V Inputs Difference from INH to INH . . . . . . . . . . . . . . . . . . . . . 5 V INH, INH . . . . . . . . . . . . . . . . . . +VS - 13.4 V, -VS + 11 V VCOM, VDUT . . . . . . . . . . . . . . . +VS - 13.1 V, -VS + 13.2 V IOL, IOH Program Voltage . . . . . . . . +VS - 15 V, -VS + 15 V Operating Temperature Range . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range . . . . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 20 sec)2 . . . . . . . +300C Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 SUGGESTED PAD LOCATION Dimensions shown in inches and (mm). Symbol IOLRTN VCOM VDUT -VS IOHRTN IOLPROG LID GND IOHPROG N/C N/C N/C +VS INH INH N/C Function Logic Low Current Return Communication Voltage Load/Dot Connection Negative Supply Logic High Current Return Logic Low Current Program Voltage Lid Connection (Internal) Ground Logic High Current Program Voltage No Connection No Connection No Connection Positive Supply Inhibit Inhibit No Connection Model AD1315KZ ORDERING GUIDE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 To ensure lead coplanarity ( 0.002 inches) and solderability, handling with bare hands should be avoided and the device should be stored in an environment at 24C, 5C (75F, 10F) with relative humidity not to exceed 65%. Temperature Range 0 to +70C Package Description 16-Lead Gull Wing Package Option* Z-16B *Z = Leaded Chip Carrier (Ceramic). REV. A -3- AD1315 DEFINITION OF TERMS Gain The measured transconductance. Gain = IOUT (@ 5V Input ) - IOUT (@ 0.2V Input ) V PROG (@ 5V ) -V PROG (@ 0.2V ) outputs are unipolar, this small initial offset of 2 mA must be set to allow for measurement of possible negative offset. With a gain of 10 mA/V, a 0.2 V input should yield an output of 2 mA. The difference between the observed output and the ideal 2 mA output is the offset error. Offset Error = IOUT (@ 0.2 V) - Gain Linearity Error where: VPROG values are measured at IOL/IOH PROG Gain Error VPROG (@ 0.2 V) The deviation of the transfer function from a straight line defined by Offset and Gain expressed as a % of FSR. IOUT (calc) = Gain VPROG (@ set point) + Offset where: set point = VPROG (from 0.2 V to 5 V) IOUT (FSR) = Gain Linearity Error The difference between the measured transconductance and the ideal expressed as a % of full-scale range. Ideal Gain = 10 mA/V Gain Error = Ideal Gain - Actual Gain x 100 Ideal Gain VPROG (@ 5 V) + Offset Offset Error IOUT (measured ) - IOUT (calc) x 100 IOUT (FSR ) Offset Error is measured by setting the IOHPROG or IOLPROG inputs to 0.2 V and measuring IOUT. Since both IOH and IOL Figure 2. Timing Diagram for Inhibit Transition Figure 1. Definition of Terms Figure 3. IOL, IOH Offset Current vs. Temperature Figure 4. IOL, IOH Gain Error vs. Temperature Figure 5. IOL , IOH Linearity Error vs. Current Program Voltage -4- REV. A AD1315 Figure 6. +IMAX, -IMAX to Inhibit Propagation Delay vs. Temperature Figure 7. Inhibit to +IMAX, -IMAX Propagation Delay vs. Temperature Figure 8. Inhibit Mode Leakage Current vs. Case Temperature Figure 9. AD1315 DC Test Circuit Figure 10. AD1315 Propagation Delay Test Circuit REV. A -5- AD1315 FUNCTIONAL DESCRIPTION The AD1315 is a complete high speed active load designed for use in general purpose instrumentation and digital functional test equipment. The function of the active load is to provide independently variable source and sink currents for the device to be tested. The equivalent circuit for the AD1315 is shown in Figure 11. An active load performs the function of loading the output of the device under test with a programmed IOH or IOL. These currents are independently programmable. VCOM is the commutation voltage point at which the load switches from source to sink mode. The active load may also be inhibited, steering current to the IOLRTN and IOHRTN pins, effectively disconnecting it from the test pin. The AD1315 accepts differential digital signals at its inhibit inputs ensuring precise timing control and high noise immunity. The wide inhibit input voltage range allows for ECL power supplies of -5.2 V and 0 V, -3.2 V and +2 V, and 0 V and +5 V. Where speed and timing accuracy are less important, TTL or CMOS logic levels may be used to toggle the Inhibit inputs of the AD1315. Single ended operation is possible by biasing one of the inputs to approximately +1.3 V for TTL or VCC/2 for CMOS. Care should be taken to observe the 4 V maximum allowable input voltage. The IOH and IOL programming inputs accept 0 V to +5 V analog inputs, corresponding to 0 to 50 mA output currents. The VCOM input, which sets the IOH/IOL switch point, may be set anywhere within the input range of -2 V to +7 V. Figure 12. Allowable Current Range for IOH, IOL vs. VDUT Ideally, the commutation point set at VCOM would provide instantaneous current sink/source switching. Because of I/V characteristics of the internal bridge diodes, this is not the case. To guarantee full current switching at the DUT, at least a 1 volt difference between VCOM and VDUT must be maintained in steady state conditions. Because of the relatively fast edge rates exhibited by typical logic device outputs, this should not be a problem in normal ATE applications. INHIBIT MODE LEAKAGE The AD1315's inhibit-mode leakage current changes with both temperature and bias levels. There are two major contributing effects: transistor reverse-bias collector-base leakage and reverse leakage in the Schottky-diode bridge. Leakage variations with VDUT arise primarily from transistor collector-base leakage, while both effects contribute to leakage current temperature variations. Inhibit-mode leakage is weakly dependent on VCOM and decreases slightly as the difference between VDUT and VCOM is reduced. Figure 8 shows typical AD1315 inhibit leakage current as a function of VDUT and temperature. THERMAL CONSIDERATIONS The AD1315 is provided in a 0.550" 0.550", 16-lead (bottom brazed) gull wing, surface mount package with a JC of 10C/W (typ). Thermal resistance (case-to-ambient) vs. air flow for the AD1315 in this package is shown in Figure 13. The data presented is for a ZIF socketed device. For PCB mounted devices (w/30 mils clearance) the thermal resistance should be ~3 to 7% lower with air flows below 320 lfm(1). Notice that the improvement in thermal resistance vs. air flow starts to flatten out just above 400 lfm(2). NOTES 1 Ifm is air flow in linear feet/minute. 2 For convection cooled systems, the minimum recommended airflow is 400 lfm. Figure 11. Block Diagram VDUT VOLTAGE RANGE In Figure 12, VDUT range, IOH and IOL typical current maximums are plotted versus DUT voltage. In the IOH mode (VDUT higher than VCOM), the load will sink 50 mA, until its output starts to saturate at approximately -1.5 V. In the IOL mode (VDUT lower than VCOM), the load will source 50 mA until its output starts to saturate at approximately +5.5 V. At +7 V, the source current will be close to zero. Figure 13. Case-to-Ambient Thermal Resistance vs. Air Flow -6- REV. A AD1315 APPLICATIONS The AD1315 has been optimized to function as an active load in an ATE test system. Figure 14 shows a block diagram illustrating the electronics behind a single pin of a high speed digital functional test system with the ability to test I/O pins on logic devices. The AD1315 active load, AD1321 or AD1324 pin driver, AD1317 high speed dual comparator and the AD664 quad 12-bit voltage DAC would comprise the pin electronic portion of the test system. Such a system could operate at 100 MHz with the AD1321 (200 MHz with the AD1324) in a data mode or 50 MHz (100 MHz) in the I/O mode. The VCOM input sets the commutation voltage of the active load. With DUT output voltage above VCOM, the load will sink current (IOH). With DUT output voltage below VCOM, the load will source current (IOL). Like the IOH and IOL return lines, the VCOM must be able to sink or source 50 mA, therefore a standard op amp will not suffice. An op amp with an external complementary output stage or a high power op amp such as the AD842 will work well here. A typical application is shown in Figure 15. LAYOUT CONSIDERATIONS IOHRTN and IOLRTN may be connected to any potential between -2 V and +7 V. These return points must be able to source or sink 50 mA, since the IOH and IOL programmed currents are diverted here in the inhibit mode. The RTNs may be connected to a suitable GND. However, to keep transient ground currents to a minimum, they are typically tied to the VCOM programming voltage point. Figure 14. High Speed Digital Test System Block Diagram Figure 15. Suggested IOHRTN, IOLRTN, VCOM Hookup REV. A -7- AD1315 EVALUATION BOARD The AD1315 Evaluation Board allows the designer to easily evaluate the performance of the AD1315 and its suitability for the specific application. The AD1315EB includes a mounted AD1315KZ active load, an ECL input buffer for Inhibit and the oscilloscope probe jacks necessary to properly analyze the true performance of the AD1315KZ. An equipment list is provided in order to minimize variations due to test setups. Figure 16. AD1315EB Evaluation Board Circuit OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Gull Wing (Z-16B) -8- REV. A PRINTED IN U.S.A. C1337a-1-5/97 |
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